1. Field of the Invention
The present invention relates to a method of fabricating dynamic random access memory (DRAM), and more particularly, to a method for improving topography/planarization of an inter layer dielectric (ILD) layer during an embedded DRAM manufacturing process.
2. Description of the Prior Art
Dynamic random access memory (DRAM) devices are used extensively in the electronics industry for information storage. A high density DRAM, such as a 64 megabit DRAM, comprises millions of memory cells. Each memory cell on the DRAM chip comprises a pass transistor, e.g. a metal-oxide-semiconductor field-effect transistor (MOSFET), and a storage capacitor for storing charge. Embedded DRAM (EDRAM) is a type of integrated circuit (IC) that combines DRAM circuits and logic circuits together in a semiconductor substrate. Nowadays, the trend in manufacturing semiconductor ICs is to integrate memory cell arrays with high-speed logic circuit elements. For example, microprocessors or digital signal processors all have integrated circuits that incorporate embedded memory.
However, the prior method of fabricating EDRAM encounters a serious topographical problem of an ILD layer before a metallization process is carried out. More specifically, the prior method encounters a problem resulting from a large difference in height on the ILD layer between a memory region and a logic region on an EDRAM. The problem of this large step height difference becomes increasingly critical for the production yield.
The steps involved in manufacturing a conventional EDRAM on a semiconductor wafer 50 are illustrated in FIG. 1 to FIG. 8. Referring first to FIG. 1, the semiconductor wafer 50 comprises a silicon substrate 52 on which a memory region 10 and a logic region 12 are previously defined. The memory region 10 comprises capacitor structures 18a, 18b and gate structures 14, while the logic region 12 comprises a plurality of gate structures 15 on the silicon substrate 52. In the memory region 10, the capacitor structures 18a, 18b are formed on an atmospheric-pressure CVD oxide (AP oxide) layer 22 having an approximately even surface. The gate structures 14, 15 are covered by a phosphosilicate glass (PSG) layer 20. A plug 16 formed in the AP oxide layer 22 and the PSG layer 20 functions to electrically connect the capacitor structure 18a and the underlying source or drain (not explicitly shown) in the silicon substrate 52.
In FIG. 1, a borophosphosilicate glass (BPSG) layer 24 acting as a buffer layer, which covers both the memory region 10 and logic region 12, is first formed on the surface of the semiconductor wafer 50. Because of the capacitor structures 18a, 18b, the difference in height on the BPSG layer 24, between the memory region 10 and the logic region 12, can be as large as 6000 to 9000 angstroms. This large difference in height (step height) can cause difficulties in forming a contact window/plug in subsequent fabrication processes and results in a more complicated fabrication problem.
Referring to FIG. 2, a conventional anisotropic dry etching process is carried out to etch the BPSG layer 24 down to the surface of the AP oxide layer 22 so as to form a spacer 26 along the rim of the memory region 10. The spacer 26 is used to release surface stress of the semiconductor wafer 50 that occurs in subsequent processes. A PSG layer 32 with a thickness of about 3000 to 7000 angstroms is then deposited on the surface of the semiconductor wafer 50. Thereafter, a thermal re-flow process is performed to reduce the step height between the memory region 10 and the logic region 12 to an extent that the difference in height is about 4000 to 8000 angstroms.
Referring now to FIG. 3, using a conventional lithographic method, a patterned and developed photoresist layer 42 is formed on the semiconductor wafer 50 to leave exposed the memory region 10 in the BPSG layer 32. An etch back process is subsequently performed to etch away a predetermined thickness from the BPSG layer that is not covered by the photoresist layer 42, leaving the remaining BPSG layer 32 about 1000 angstroms thick over the memory region 10. A photoresist ashing process and a series of cleaning procedures are then carefully carried out to remove the photoresist layer 42 and obtain a clean semiconductor wafer surface.
In FIG. 5, a conventional chemical mechanical polishing (CMP) process is performed to planarize the BPSG layer 32. The CMP process must be carried out with extreme care to prevent breakthrough of the BPSG layer 32 over the capacitor structures 18a, 18b. Next, as shown in FIG. 6, a PSG layer 44 with a thickness of about 1000 angstroms is deposited using a conventional chemical vapor deposition technique to form a more even surface.
In FIG. 7, by means of a conventional lithographic technique and a dry etching process, a contact plug 46 is formed over in the PSG layer 44, AP oxide layer 22 and PSG layer 20 to the surface of the silicon substrate 52 over the logic region 12. The contact plug 46 is used to electrically couple with the subsequently formed upper layer metal and the underlying devices on the silicon substrate 52. Finally, as shown in FIG. 8, a metal layer 48 is formed atop the PSG layer 44, thereby completing the fabrication of a conventional EDRAM.
From the above, the prior method of fabricating EDRAM has the following drawbacks: (1) the spacer 26 used to release stress is required in the prior art process; (2) an additional BPSG layer 24 and an etching process are therefore needed to form the spacer 26; (3) an additional thick PSG layer 32 is required; (4) an additional thermal re-flow process is required to obtain a smoother PSG layer 32; (5) an additional lithographic process and an etching process are needed to remove a predetermined thickness of the PSG layer 32 over the memory region 10; and (6) an extra-expensive CMP process is also needed. Consequently, the prior art method of fabricating EDRAM is inefficient, time-consuming and costly.